VLSI IEEE Project 2013 – 2014


In the realm of electronics and semiconductor design, the years 2013-2014 marked a pivotal era as IEEE Project Centre introduced a diverse range of VLSI IEEE Projects. These projects, meticulously crafted to align with the esteemed standards of the Institute of Electrical and Electronics Engineers (IEEE), provided an exceptional platform for students and professionals to delve into the intricacies of Very Large Scale Integration (VLSI).

Throughout the 2013-2014 period, IEEE Project Centre showcased a spectrum of VLSI projects, each thoughtfully designed to explore various dimensions of VLSI design. From low-power design and hardware security to digital signal processing and emerging technologies, participants were immersed in hands-on experiences that seamlessly integrated theoretical knowledge with real-world applications. These projects not only honed technical skills but also nurtured critical problem-solving abilities, all while adhering to the rigorous benchmarks set by IEEE.


Collaboration with industry experts and mentors within the IEEE Project Centre offered participants an unparalleled opportunity to dive deep into the world of VLSI design. These projects tangibly showcased the practical outcomes of theoretical concepts, equipping participants with an in-depth understanding of VLSI’s principles and capabilities. The result was a cohort of individuals exceptionally prepared to address contemporary challenges, standing on the foundation fortified by the 2013-2014 VLSI IEEE projects at the IEEE Project Centre.


In conclusion, the years 2013-2014 underscore the IEEE Project Centre’s commitment to nurturing innovation and knowledge in the realm of VLSI design, aligning with the highest standards of the IEEE. By providing a platform for immersive exploration, collaboration with experts, and adherence to the stringent criteria set by IEEE, these projects have enriched participants’ technical acumen while fostering a mindset of innovation and adept problem-solving. As we stride ahead, the impact of the 2013-2014 VLSI IEEE projects continues to resonate, shaping participants’ academic and professional journeys in profound and transformative ways.


SNOProjects List
1Graph-Based Transistor Network GenerationMethod for Supergate Design
2Implementing Minimum-Energy-Point SystemsWith Adaptive Logic
3Approximate Radix-8 Booth Multipliers for Low-Power and High-Performance Operation
4A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications
5The Serial Commutator (SC) FFT
7An Improved Signed Digit Representation Approach for Constant Vector Multiplication
8High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels
9A New XOR-Free Approach for Implementation of Convolutional Encoder
10Energy and Area Efficient Three-Input XOR/XNORs With Systematic Cell Design Methodology
11Approximate Radix-8 Booth Multipliers for Low-Power and High-Performance Operation
12Implementation of a PID control PWM Module on FPGA
13Built-in Self Testing of FPGAs
14An FPGA-Based Cloud System for Massive ECG Data Analysis
15Distributed Sensor Network-on-Chip for Performance Optimization of Soft-Error-Tolerant Multiprocessor System-on-Chip
16VLSI Implementation of Fully Parallel LTE Turbo Decoders
17A High Throughput List Decoder Architecture For Polar Codes
18High-Performance NB-LDPC Decoder With Reduction of Message Exchange
19A High-Speed FPGA Implementationof an RSD-Based ECC Processor
20Low-Power ECG-Based Processor forPredicting Ventricular Arrhythmia
21In-Field Test for Permanent Faults in FIFO Buffers of NoC Routers
22Configurable Parallel Hardware Architecture forEfficient Integral Histogram Image Computing
23Input-Based Dynamic Reconfiguration of Approximate Arithmetic Units for Video Encoding
24A Normal I/O Order Radix-2 FFT Architecture to ProcessTwin Data Streams for MIMO
25Unequal-Error-Protection Error Correction Codes for theEmbedded Memories in Digital Signal Processors
26Hybrid LUT/Multiplexer FPGA Logic Architectures
27A Dynamically Reconfigurable Multi-ASIP Architecture forMultistandard and Multimode Turbo Decoding
28Low-Power Split-Radix FFT Processors Using Radix-2 Butterfly Units
29A Fully Digital Front-End Architecture for ECGAcquisition System With 0.5 V Supply
30A Low-cost and Modular Receiver for MIMO SDR
31High-Speed, Low-Power, and Highly Reliable Frequency Multiplier for DLL-Based Clock Generator
32Frequency-Boost Jitter Reduction forVoltage-Controlled Ring Oscillators
33Low-Energy Power-ON-Reset Circuit for Dual Supply SRAM
34Low-Power Variation-Tolerant Nonvolatile Lookup Table Design
35A Low-Power Robust Easily CascadedPentaMTJ-Based Combinational and Sequential Circuits
36A 0.1–3.5-GHz Duty-Cycle Measurement andCorrection Technique in 130-nm CMOS
37Full-Swing Local Bitline SRAM ArchitectureBased on the 22-nm FinFET Technology for Low-Voltage Operation
38A Robust Energy/Area-Efficient Forwarded-ClockReceiver With All-Digital Clock and Data Recovery in 28-nm CMOS for High-Density Interconnects
39OTA-Based Logarithmic Circuit for ArbitraryInput Signal and Its Application
40A Single-Ended With Dynamic Feedback Control8T Subthreshold SRAM Cell