VLSI IEEE Project 2014 – 2015


VLSI Comes There Square Measure 2 Differing Kinds Of 2014 And 2015 IEEE Project Centers Potentialities Particularly Comes In VLSI Primarily Based System Style And VLSI Style Itself. Most Students Don’t Perceive The Distinction Between The 2, However There’s A Really Important Distinction Between The 2. Comes In VLSI Style Square Measure Comes That Modify The Semiconductor Style, These Square Measure Most Frequently Than Not Solely Restricted To Simulation And Square Measure Terribly Troublesome And High-Ticket To Implement As Real Time Comes.

Projects In VLSI Primarily Based System Style Square Measure Comes That Involve The Look Of Varied Varieties Of Digital Systems That May Be Enforced On A PLD Device Sort Of A FPGA Or A CPLD. For Instance The Look Of A Encoder, Decoder Or A ALU Etc Square Measure Digital System Styles That May Be Enforced On A FPGA. 2014 2015 IEEE Project Centers Chennai Similar Digital Systems, But Of A Additional Advanced Nature May Be Enforced As A Final Year Project In VLSI. These May Be Supported Any Of The Favored High-Density Lipoprotein Languages Like VHDL Or Verilog. Each VHDL Comes And Verilog Comes Square Measure Sensible Decisions For Comes.

Another Recent Trend In VLSI Comes For BE, B School And Even Additional Suited To Maine, M School Comes Square Measure Comes Supported Soft Core Processors Like NIOS II Or Xilinx Microblaze And Similar Soft Core Processors. We Tend To At Ingens Extremely Suggest Such Comes, As A Result Of They Permit The Implementation Of Advanced Digital Systems With Relative Ease And Thus Create Wonderful Decisions For Final Year Comes.


SNO Projects List
1 Graph-Based Transistor Network GenerationMethod for Supergate Design
2 Implementing Minimum-Energy-Point SystemsWith Adaptive Logic
3 Approximate Radix-8 Booth Multipliers for Low-Power and High-Performance Operation
4 A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications
5 The Serial Commutator (SC) FFT
7 An Improved Signed Digit Representation Approach for Constant Vector Multiplication
8 High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels
9 A New XOR-Free Approach for Implementation of Convolutional Encoder
10 Energy and Area Efficient Three-Input XOR/XNORs With Systematic Cell Design Methodology
11 Approximate Radix-8 Booth Multipliers for Low-Power and High-Performance Operation
12 Implementation of a PID control PWM Module on FPGA
13 Built-in Self Testing of FPGAs
14 An FPGA-Based Cloud System for Massive ECG Data Analysis
15 Distributed Sensor Network-on-Chip for Performance Optimization of Soft-Error-Tolerant Multiprocessor System-on-Chip
16 VLSI Implementation of Fully Parallel LTE Turbo Decoders
17 A High Throughput List Decoder Architecture For Polar Codes
18 High-Performance NB-LDPC Decoder With Reduction of Message Exchange
19 A High-Speed FPGA Implementationof an RSD-Based ECC Processor
20 Low-Power ECG-Based Processor forPredicting Ventricular Arrhythmia
21 In-Field Test for Permanent Faults in FIFO Buffers of NoC Routers
22 Configurable Parallel Hardware Architecture forEfficient Integral Histogram Image Computing
23 Input-Based Dynamic Reconfiguration of Approximate Arithmetic Units for Video Encoding
24 A Normal I/O Order Radix-2 FFT Architecture to ProcessTwin Data Streams for MIMO
25 Unequal-Error-Protection Error Correction Codes for theEmbedded Memories in Digital Signal Processors
26 Hybrid LUT/Multiplexer FPGA Logic Architectures
27 A Dynamically Reconfigurable Multi-ASIP Architecture forMultistandard and Multimode Turbo Decoding
28 Low-Power Split-Radix FFT Processors Using Radix-2 Butterfly Units
29 A Fully Digital Front-End Architecture for ECGAcquisition System With 0.5 V Supply
30 A Low-cost and Modular Receiver for MIMO SDR
31 High-Speed, Low-Power, and Highly Reliable Frequency Multiplier for DLL-Based Clock Generator
32 Frequency-Boost Jitter Reduction forVoltage-Controlled Ring Oscillators
33 Low-Energy Power-ON-Reset Circuit for Dual Supply SRAM
34 Low-Power Variation-Tolerant Nonvolatile Lookup Table Design
35 A Low-Power Robust Easily CascadedPentaMTJ-Based Combinational and Sequential Circuits
36 A 0.1–3.5-GHz Duty-Cycle Measurement andCorrection Technique in 130-nm CMOS
37 Full-Swing Local Bitline SRAM ArchitectureBased on the 22-nm FinFET Technology for Low-Voltage Operation
38 A Robust Energy/Area-Efficient Forwarded-ClockReceiver With All-Digital Clock and Data Recovery in 28-nm CMOS for High-Density Interconnects
39 OTA-Based Logarithmic Circuit for ArbitraryInput Signal and Its Application
40 A Single-Ended With Dynamic Feedback Control8T Subthreshold SRAM Cell