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SNOProjects List
1Energy efficient reduce and rank using input adaptive approximations
2Enfire: a spatio-temporal fine-grained reconfigurable hardware
3Sign-magnitude encoding for efficient vlsi realization of decimal multiplication
4Adaptive multibit crosstalk-aware error control coding scheme for on-chip communication
5Dual-quality 4:2 compressors for utilizing in dynamic accuracy configurable multipliers
7A way-filtering-based dynamic logical–associative cache architecture for low-energy consumption
8Resource-efficient sram-based ternary content addressable memory
9A high-efficiency 6.78-mhz full active rectifier with adaptive time delay control for wireless power transmission
1High-speed and low-latency ecc processor implementation over gf(2m) on fpga
2A 2.5-ps bin size and 6.7-ps resolution fpga time-to-digital converter based on delay wrapping and averaging
3Comedi: combinatorial election of diagnostic vectors from detection test sets for logic circuits
4Low-power scan-based built-in self-test based on weighted pseudorandom test pattern generation and reseeding
5A 2.4–3.6-ghz wideband sub-harmonically injection-locked pll with adaptive injection timing alignment technique
6fast automatic frequency calibrator using an adaptive frequency search algorithm
7A 65-nm cmos constant current source with reduced pvt variation
8High-speed parallel lfsr architectures based on improved state-space transformations
9Scalable approach for power droop reduction during scan-based logic bist
10Soft error rate reduction of combinational circuits using gate sizing in the presence of process variations
11Stochastic implementation and analysis of dynamical systems similar to the logistic map
1Roba multiplier: a rounding-based approximate multiplier for high-speed yet energy-efficient digital signal processing
2Vlsi design of 64bit × 64bit high performance multiplier with redundant binary encoding
3A method to design single error correction codes with fast decoding for a subset of critical bits
4Hybrid hardware/software floating-point implementations for optimized area and throughput tradeoffs
5Efficient soft cancelation decoder architectures for polar codes
6Low-complexity digit-serial multiplier over gf(2m) based on efficient toeplitz block toeplitz matrix–vector product decomposition
7Efficient designs of multiported memory on fpga
8Hybrid lut multiplexer fpga logic architectures
9Fpga realization of low register systolic all-one-polynomial multipliers over gf (2m) and their applications in trinomial multipliers
10Coordinate rotation-based low complexity k-means clustering architecture
11Energy-efficient vlsi realization of binary64 division with redundant number systems
12Hardware-efficient built-in redundancy analysis for memory with various spares
1A dual-clock vlsi design of h.265 sample adaptive offset estimation for 8k ultra-hdtv encoding


1Multicast-aware high-performance wireless network-on-chip architecturesDownload
2Scalable device array for statistical characterization of bti-related parameters
3Write-amount-aware management policies for stt-ram caches
4Temporarily fine-grained sleep technique for near- and subthreshold parallel architectures
5Low-power design for a digit-serial polynomial basis finite field multiplier using factoring technique
6Analysis and design of a low-voltage low-power double-tail comparator
7Sense amplifier half-buffer (sahb): a low-power high-performance asynchronous logic qdi cell template
8A 0.45 v 147–375 nwecg compression processor with wavelet shrinkage and adaptive temporal decimation architectures
910t sram using half-vddprecharge and row-wise dynamically powered read port for low switching power and ultralow rbl leakage
10A single channel split adc structure for digital background calibration in pipelined adcs
11Energy-efficient tcam search engine design using priority-decision in memory technology
12A 92-db dr, 24.3-mw, 1.25-mhz bw sigma–delta modulator using dynamically biased op amp sharing
13On micro-architectural mechanisms for cache wear out reduction
14Low-complexity transformed encoder architectures for quasi-cyclic non-binary ldpc codes over subfields